`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   20:12:41 11/28/2012
// Design Name:   ACC_UNIT
// Module Name:   D:/Workspace/xilinx workspace/HFM_DETECTOR/acc_simu.v
// Project Name:  HFM_DETECTOR
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: ACC_UNIT
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module acc_simu;

	// Inputs
	reg clk;
	reg rst;
	reg [32:0] a_r;
	reg [32:0] a_i;

	// Outputs
	wire [36:0] out_r;
	wire [36:0] out_i;
	integer i;
	always #10 clk = ~clk;
	// Instantiate the Unit Under Test (UUT)
	
	ACC_UNIT #(4, 16, 33) uut (
		.clk(clk), 
		.rst(rst), 
		.a_r(a_r), 
		.a_i(a_i), 
		.out_r(out_r), 
		.out_i(out_i)
	);

	initial begin
		// Initialize Inputs
		clk = 0;
		rst = 0;
		a_r = 0;
		a_i = 0;

		rst = 1;
        
		// Add stimulus here
		for(i=0;i<50;i=i+1)
			#20 
			begin
			a_r = i;
			a_i = 1;
			end

	end
      
endmodule

